1. Переведите подзаголовки описания изобретения
1. Field of the Invention
2. Background of the Invention
3. Summary of the Invention
4. Brief Description of the Drawings
5. Description of the Preferred Embodiment
2. Переведите предложения, содержащие штампы, относящиеся к области изобретения.
1. The invention relates to semi-conductive devices, for example transistors or crystal diodes. 2. The present invention is concerned with a novel geophone assembly adapted for use in bore holes in the earth's substrata. 3. This invention deals with electrical coupling circuits or high frequency signals especially in the UHF range. 4. This invention has to do with improvements relating ,to the cooling of rectifiers, transistors and like semiconductor devices, but especially germanium and silicon , rectifiers. 5. This invention refers to seismic prospectling.
3. Переведите предложения, содержащие штампы, относящиеся к целям изобретения.
1. The leading object of the present invention is to provide an improved device of the type described. 2. The object of the present invention is to provide cooling means for the brake shoes and linings thereof. 3. It is the general object of this invention to provide a method of making an electroluminescent phosphor. 4. One of, the objects of the invention is to suppress transmission of vibrations or shock waves along cable of the geophone device. 5. An object of the present invention is to provide a setscrew which is simple and inexpensive to manufacture.
4. Переведите предложения, содержащие штампы, относящиеся к сущности изобретения.
1. According to the invention there is provided a luminous sign consisting of a panel on which letters, numerals or other symbols or outlines are formed. 2. According to the present invention there is provided an X-ray intensifying screen consisting of a binding means, ' a luminescent material and a dyestuff colloidally distributed in said means. 3. According to this invention a ; two-speed mechanical drive mechanism of the kind referred to comprises a threaded shaft, a worm screwed upon said shaft, and limiting stops. 4. According to the invention there is provided a Hall generator device, comprising a Hall generator intended to be subjected to a magnetic field acting in one particular direction. 5. In carrying out the objects of the present invention, an air conditioner is provided comprising a refrigerator system with an evaporator, a compressor and a condenser.
5. Переведите предложения, содержащие штампы, относящиеся к описанию изобретения со ссылкой на прилагаемые чертежи.
1. The invention will now be described more fully by way of example, with reference to one embodiment thereof, which is illustrated in the accompanying diagrammatic drawing in which the figure shows a longitudinal section of a transistor. 2. To illustrate the above statements, reference will be made to the attached drawings, Fig. 1 of which shows a cross-sectional elevation of the device. 3. The invention will now be more particularly described with reference to the accompanying drawings which show a plan of a chassis of a motor vehicle constructed according to this invention. 4. Some embodiments of the invention will now be described by way of example, reference being made to the accompanying drawings, in which... 5. For the better understanding of the invention, reference may be had to the accompanying drawings in which...
6. Переведите предложения, содержащие расширяющие разделы.
1. The invention is not limited to the exact forms of setscrew illustrated in the accompanying drawings and specification, various changes in the detail of construction may be resorted to by those skilled in the art without departure from the scope of the invention. 2. Other objects and features of the invention will appear from a detailed study of the drawings. 3. Other objects and features of the invention will appear as the description of the particular physical embodiment selected to illustrate the invention progresses. 4. It is therefore desired that the invention be not limited to the specific embodiment shown and described and it is intended to соver in the appended claim all such modifications that f all within the true spirit and scope of the invention. 5. The invention hereinabove described may be varied i-in construction within the scope of the claim, for the particular device selected to illustrate the invention is but one of many possible embodiments of the same.
7. Переведите следующие фрагменты описаний изобретений к патентам.
1. Complete Specification filed Oct. 10, 1991. 2. Application 6598/87 filed May 7, 1987. 3. Index at acceptance: C1-IZ5T. 4. The Present invention pertains to , abrasive articles. 5. The present invention aims at improving the accuracy of the machine tool. 6. In my present invention I provide a signal for marking the position of the electric transmission line serving to assist the aviator in locating the transmission line during the night and during foggy weather, when the visibility is poor. 7. According to the invention the cultivator comprises a handle portion, an electric motor, a crossshaft and a wheel with ground cultivating teeth.
8. Выполните перевод технической документации, в частности технического задания на разработку голограмм.
General Director of the Joint Venture “HI”
Pharmaceutics enterprise “EBEWE” 2000
for development and production of “Cerebrolysin” holograms
Field of application (use) of the product: The hologram is designed to be attached to an item as a sign providing protection against forgery as well as to certify quality of the product.
Basis for development: Agreement between the Parties.
Executor: Joint Venture “HI”.
Producer: Joint Venture “HI”.
Goal and purpose of development: Visualization and possibility of identification for a wide circle of users as well as identification of products by means of special devices.
Financial source: The work is financed in accordance with the contract signed.
Composition of products and design requirements: The hologram should be prepared by a combined method: the part made by the DOT-MATRIX technology should be a Cerebrolysin cinergam approved by the customer. The other part should be a latent image in the form of “OK”. The hologram should have a latent image throughout the surface area. The hologram should have three colours with the lattice constant from 500 to 1000 lines/mm. Local microdefects are admissible whose size does not exceed 1 mm and whose total area does not exceed 1 % of the total area of the hologram. The hologram should correspond to the approved design (see Appendix 1). Each hologram should have its own number which is a series consisting of one Latin letter and six numerals. Numbers are arranged in accordance with the approved design (see Appendix 1).
Reliability requirements: The hologram should be time-resistant to the action on it of normal usage factors complying with the usage conditions, and in the event of unauthorized interventions it should break down and be unable to be transferred onto other objects, documents. The service life corresponds to that of the preparation Cerebrolysin.
Safety and ecological requirements: The technology for production of holograms should provide safe working conditions. The hologram should conform with the sanitary and ecological standards that are in force in the territory of the Republic of Belarus.
Aesthetic requirements: In accordance with the design approved by the Buyer.
Requirements for products’ components (if any), source and usage materials: the foil, release paper, and glue should provide:
readability of the image approved for production of holograms after they are applied to a product. No magnification is required for normal vision, the range of the tilt angle, at which the peculiarities indicated in subpoint 7.1 are revealed when the image is being viewed is within the limits of ± 30° counted from the perpendicular to the hologram surface; reliable attachment of the hologram to a product; the foil should break down at an attempt to remove and transfer the hologram.
Usage conditions: To transfer the hologram onto a package, it should be removed from the release paper and sticked by the labelling machine onto the package at a temperature from 10 to 35°.
Marking and packaging requirements: The hologram should be supplied in webs with the inside diameter of the bobbin 76 mm, the outside maximum diameter of the web 330 mm. The hologram arrangement in a web shall be performed according to Appendix 2. Each web should have a label bearing the following data: number of holograms with indication of the range of numbers, date of fabrication, period of storage of holograms and lot number. The period of storage is 6 months from the date of delivery to the Buyer at normal storage.
Transportation and storage requirements: A package with holograms should not be subject to shocks, exposed to moisture and high temperatures. Storage conditions: temperature from +5 to +20 °C, humidity 50-70%.
Development phases and stages:
logotype approval by the Buyer;
production of originate hologram on a photoresistor;
holographic specimen approval by the Buyer;
fabrication of the matrix;
fabrication of a trial lot in the amount of 10 000 holograms;
delivery of the trial lot and test on the Buyer’s equipment;
Control method and accepting procedure, materials submitted on completion of separate phases (stages) and work as a whole: Quality and quantity control is exercised after each operation. Results are registered in the journal of routine accounting of semifinished items and in operation logs, whereupon products are transferred to further operations.
Requirements for commercial secret guarantee: Commercial secret for executing orders is insured in accordance with internal regulations: “Regulations for guaranteeing commercial secret of the enterprise” and “Regulations for creating special conditions for safety of confidential information, raw materials
and finished products during the execution of orders for holographic elements of protection, special marks and correspondence signs”, as well as with instructions issued in development of the above regulations.
Note: Additions and changes can be introduced into this Technical Assignment upon consultations.
9. Выполните перевод патента США. Патент представлен в сокращенной форме, лишь основные его части, так как полный размер патента 49 страниц.
United States Patent 6,751,583
Clarke , et al. June 15, 2004
Hardware and software co-simulation including simulating a target processor using binary translation
Inventors: Clarke; Neville A. (Quorrobolong, AU); Torossian; James R. (Whale Beach, AU) Assignee: VaST Systems Technology Corporation (Sunnyvale, CA)
Appl. No.: 933579 Filed: August 20, 2001
Current U.S. Class: 703/17; 703/19; 703/20; 703/22; 717/127
Intern. Class: G06F 009/455; G06F 017/50
Field of Search: 703/13,14,17,19,6,22,27,28 716/3,18 717/104,127
A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program. The timing information incorporates target processor instruction timing. Adding of timing information includes inserting dynamic hooks into the host code that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution such that while the processor simulator executes the analyzed version of the user program, the processor simulator accumulates simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing as if the user program was executing on the target processor.
FIELD OF THE INVENTION
The present invention relates to computer software and hardware simulators, and more specifically, to a system and method to simulate an electronic system that includes one or more target processors executing software and interacting with hardware.
Computer simulation of digital hardware systems has become a common technique to reduce the cost and time required for the design of such hardware systems. Simulating digital hardware allows a designer to predict the functioning and performance of the hardware prior to fabricating the hardware.
More and more digital systems incorporate a processor, including a microprocessor, a digital signal processor, or other special purpose computer processor. There has been increased effort to develop a simulation system that includes simulating the hardware and simulating the running of software on one or more processors that are included in the digital system. Having such a simulation system allows a designer to test the operation of software on the processor(s) before a physical processor is available. Thus, for example, a designer may be able to start designing a system incorporating a new microprocessor before the manufacturer actually releases physical samples of the microprocessor. In addition, a system designer designing an integrated circuit or a system on a printed circuit board that includes a processor can, for example, use the simulation system to test the integrated circuit or printed circuit board implementation, including operation of software on the processor part, and any testing interactions between the processor and the other digital circuit elements of the integrated circuit or board, before the integrated circuit or board is fabricated. This clearly can save time and money.
A simulation system for simulating both the digital hardware that includes one or more target processors and the running of software on the processor(s) is called a cosimulation design system, a co-simulation system, or simply a design system herein, and the environment for operating such a co-simulation system is called a design environment. The processor is called a target processor and the computer system on which the environment operates is called the host computer system or simply the host. The host computer system includes one or more host processors. The hardware other than the target processor is called digital circuitry. The computer software program that is designed by a user to operate on the target processor is called the user program or the target code.
The target processor typically includes memory and one or more caches, for example a data cache (or D-cache) and an instruction cache (or I-cache). The target processor typically may also include a memory management unit (MMU) that converts virtual addresses into physical memory addresses and possibly physical I/O device addresses. The MMU may include a translation lookaside buffer (TLB) to improve address translation performance. A TLB is a hardware element that acts as a cache of recent translations and stores virtual memory page to physical memory page translations. Given a memory address (an instruction to fetch, or data to load or store), the target processor first looks in the TLB to determine if the mapping of virtual page to physical page is already known. If so (a “TLB Hit”), the translation can be done quickly. But if the mapping is not in the TLB (a “TLB Miss”), the correct translation needs to be determined.
The target processor may be a separate microprocessor with the digital circuitry being external to the microprocessor (e.g., on a printed circuit board or elsewhere in the system), or may be a processor embedded in an application specific integrated circuit (ASIC) or a custom integrated circuit (IC) such as a very large scale integrated (VLSI) device, with the digital circuitry including some components that are part of the ASIC or IC, and other components that are external to the ASIC or IC.
The host processor also includes memory, and the host memory is referred to as “host memory” herein. The physical address of the host memory is referred to as the “host address” herein. When the word “address” is used without specifying the host, then it refers to the target address.
Furthermore, while the description has concentrated on a co-design system and simulation method that simulates an electronic system that has one target processor, the system and method are applicable to having more than one target processor, and each can be a different processor.
Furthermore, while the physical to host memory mapping is represented by a linked list, other memory allocation data structures such as an array may be used.
Note that the HINT data structure in one embodiment is part of the HCB. In another embodiment, the HINT data structure, or the contents thereof, can be stored elsewhere, but associated with the HCB or the relevant part thereof. Furthermore, different parts of the HINT data structure may be stored at different locations.
The description uses the term “pointer.” A pointer in this context includes any mechanism that directs the simulator to a location.
Therefore, although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that the disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those of ordinary skill in the art after having read the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.